1. Field of the Invention
The present invention relates generally to microelectronic circuits, and more particularly, to power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) circuits having high packing densities.
2. Description of the Related Art
Power semiconductor devices have long been used as replacement for mechanical relays in various applications. Development in semiconductor technology enables these power devices to operate with high reliability and performance. FIG. 1 shows a conventional MOSFET (Metal Oxide Semiconductor Field Effect Transistor) array arranged on a planar configuration. The MOSFET array is generally signified by the reference numeral 2. The array 2 comprises a substrate 4 which is deposited with various diffusion or implant regions. For example, there are source regions 6 which are heavily doped with N-type material. Similarly, there are body regions 8 which are doped with P-type material. The drain 9 comprises an epitaxial layer 10 deposited in contact with a heavily doped drain contact layer 12 formed of N-type material. A plurality of polysilicon gates 14 is also disposed above the substrate 4 spaced by gate oxide layers 16. The polysilicon gates 14 are electrically connected together via bridging traces not shown in FIG. 1. Similarly, the sources 6 are electrically tied together via a source metal layer 17.
During normal operations, the sources 6 are connected to the ground potential via the source metal layer 17. At the same time, a positive potential is applied across the drain 9 and the source regions 6. A drain-to-source voltage V.sub.DS is established. In a similar fashion, a gate-to-source voltage V.sub.GS is also applied across the gates 14 and the source regions 6. The V.sub.GS voltage capacitively induces N-type channels 18 underneath the gate oxide layers 16. The channel 18 allows the V.sub.DS voltage to drive a drain-to-source current I.sub.DS from the drain 9 to the source regions 6. The MOSFET 2 is said to be at the power-on state.
The current path where the drain-to-source current I.sub.DS flows is predominantly resistive and the resistance value is called the drain-to-source R.sub.DS of the MOSFET. In a power MOSFET device, there is a plurality of individual MOSFETs 19 fabricated together to form the MOSFET array 2. The aggregate resistance values of the drain-to-source resistance R.sub.DS during the power-on state is called the power-on resistance R.sub.ON of the MOSFET array 2.
It has been a constant design goal to make MOSFET arrays with low power-on resistance R.sub.ON. Lower power-on resistance R.sub.ON not only curtails power consumption and thus cuts down the wasteful heat dissipation of the MOSFET array 2, it also prevents the MOSFET array 2 from robing away any intended driving voltage V.sub.CC to any circuits that the MOSFET array 2 drives. Specifically, lower Ohmic drop passing through the MOSFET array 2 during normal operations avails any circuits driven by the MOSFET 2 with a less distorted driving voltage V.sub.CC.
The advent of high resolution photolithography allows semiconductor components to be formed on a semiconductor substrate with ultra fine geometries. Accordingly, to reduce the power-on resistance R.sub.ON of any MOSFET arrays, one conventional approach is to densely integrate the MOSFETs 19 on the semiconductor substrate 4. The rationale behind this approach is that the higher the number of MOSFETs 19 operating in parallel, the lower the overall power-on resistance R.sub.ON results in the MOSFET array 2. However, theoretical feasible as it appears, there are various technical complications associated with densely integrating a planar MOSFET array 2.
Reference is now directed back to FIG. 1 which shows the countervailing factors commonly frustrating the attempts of densely integrating a planar MOSFET device. As mentioned before, advanced development in high definition photolithography allows denser device integration. As integration density increases, cell-to-cell separations decrease. As shown in FIG. 1, the drain-to-source resistance R.sub.DS of each cell during the power-on state can be approximated by the following algebraic equation: EQU R.sub.DS =R.sub.cs +R.sub.S +R.sub.ch +R.sub.j +R.sub.d1 +R.sub.d2(1)
where R.sub.CS is the contact resistance of the source metal 17 to the source region 6; R.sub.s is the source resistance; R.sub.ch is the channel resistance; R.sub.j is the junction resistance; R.sub.d1 is the drain resistance at the epitaxial region 10; and R.sub.d2 is the drain resistance at the drain contact region 12 in ohms. The dominant components are the junction resistance R.sub.j and the drain resistance R.sub.d1 at the epitaxial region 10. First, the epitaxial layer 10 is lightly doped and consequently assumes a high resistivity. Furthermore, the epitaxial region 10 is also a relatively thick layer and therefore extends a longer resistive path. As integration density increases, the diffusion regions, such as the source diffusion regions 6 and the body diffusion regions 18 among the MOSFET cells 2 encroach closer and closer toward each other as illustrated by the directions 20 shown in FIG. 1. Consequently, during the power-on state, the drain-to-source current I.sub.DS of each cell only has a limited resistive area to pass through. As shown in FIG. 1, basically, the region signified by the reference numeral 22 has to be shared by two MOSFET cells 19. As is known in the art, the smaller the area of the resistive path, the higher is the resistance value. Equally as detrimental is the current crowding effect in the confined region 22 which also plays a dominant role in increasing the values of the resistances R.sub.j and R.sub.d1. Accordingly, the advantage gained in pursuing higher density integration can be totally negated by the increase in drain and junction resistances R.sub.d1 and R.sub.j as explained above.
To avoid the aforementioned problems associated with dense integration, MOSFET structures with trenched gates have been devised. FIG. 2 shows a typical arrangement of trenched MOSFET array signified by the reference numeral 24 which includes a substrate 26. There is a plurality of trenches 28 filled with conducting material 30 which is electrically separated from the substrate 26 by a thin insulting layer 32. Each MOSFET cell 34 can be a N-channel device comprising a source layer 36 made of N-type material; a body layer 38 formed of P-type material; an epitaxial layer 40 composed of a lightly doped N-type material; and a drain contact layer 42 based on a heavily doped N-type material. Atop the trenches 28 are insulating layers 42 insulating the conductive material 30 from a source contact metal layer 17. There is also a drain metal contact layer 46 attached to the drain contact region 42 of the MOSFET 24. The conductive materials 30 in the trenched gates 28 are electrically connected together but are not shown in FIG. 2.
There are also cell contact regions 52 diffused in the substrate 26. The implementation of the cell contact regions 52 is to prevent triggering the parasitic NPN transistors 54 into action, which NPN transistors 54 are surreptitiously embedded in each MOSFET cell 34. As shown in FIG. 2, the source region 36 is of N-type which corresponds to the emitter E of the NPN transistor 54. Similarly, the body region 38 is of P-type conductivity which acts as the base B of the NPN transistor 24. The N-type drain 42 is the common collector of all the transistors 54 (only one is shown in FIG. 2). The body regions 38 are lightly doped regions and assume high resistivity. In accordance with Ohm's law, current passing through any resistive body region 38 generates a potential voltage difference. With the body regions 38 built in with a high resistivity, small amount of stray current passing through the regions 38 will suffice to generate a voltage of sufficient magnitude to turn on the base-to-emitter voltages V.sub.BE of the NPN transistors 54. Once the parasitic transistors 54 are turned on, they enter into the active conduction mode and sustain huge collector-to-emitter current I.sub.CE and cause irreparable damages to the MOSFET cells 34.
The presence of the cell contact regions 52 is to decrease the base-to-emitter resistivity of the NPN transistors 54 such that they can tolerate a reasonably high base-to-emitter current without exceeding the typical base-to-emitter voltage V.sub.BE which is about a potential difference drop of a diode of approximately 0.7 Volts.
As with the planar MOSFET array 2 shown in FIG. 1, the current path where the drain-to-source current I.sub.DS flows is resistive and its resistance is called the drain-to-source R.sub.DS of the MOSFET cell 34. The aggregate resistance values of the drain-to-source resistance R.sub.DS during the power-on state is called the power-on resistance R.sub.ON of the MOSFET array 24. Since the channels 48 are arranged in a vertical manner, the lateral current paths are basically eliminated. The problem of cell-to-cell encroachment competing for current flow is no longer an issue. That is, as different from the MOSFET array 2 with the planer configuration, the junction resistance R.sub.j of the drain-to-source resistance R.sub.DS is essentially removed, as shown in FIG. 2. Moreover, the drain resistance R.sub.d1 in the epitaxial region 40 also has a relatively larger cross-sectional area for current to pass through due to the more spaced-apart relationship between the cells 34. The consequential benefit is that a higher degree of integration on a semiconductor substrate can be realized, which in turn provides lower power-on R.sub.ON resistance. Lower power-on resistance R.sub.ON curtails ohmic loss during the power-on state and further alleviates heat dissipation.
Advantageous as it appears, densely integrating the cells 34 necessitates packing more cells 34 per unit area on a semiconductor surface. As a consequence, each cell 34 is laid out with a smaller physical area having smaller contact surfaces for the source regions 36 and for the cell contact regions 52. Accordingly, cross-sectional areas for current flow through the regions 36 and 52 are also diminished resulting in increase in contact resistivity. Differently put, with reference to FIG. 2, the source contact resistance R.sub.CS and the cell contact resistance R.sub.CC of each cell 34 are increased due to the corresponding decrease in the individual geometrical areas of the source region 36 and the cell contact region 52 because of the overall reduction in area of each cell 34. As a consequence, the cell contact regions 52 are less effective in suppressing the parasitic transistors 54 during normal operations. Equally as undesirable is that the source contact resistance R.sub.CS, and to a lesser extent, the source resistance R.sub.s in the source regions 36, emerge as the dominant components in the drain-to-source resistance R.sub.DS of the MOSFET 24 during the power-on state.
Thus, scaling down the geometrical areas of the cells in a MOSFET array does not appear to be a viable solution to reduce the power-on resistance R.sub.ON of the MOSFET array fabricated via high density integration. There is a minimum limit in cell area that each cell 34 must maintain. Beyond such a limit, the dominant effects of the source contact resistance R.sub.CS and the cell contact resistance R.sub.CC would negate any advantages of fabricating MOSFET arrays by way of high density integration.
Prior to any further analysis, the configurations of the conventional MOSFET arrays need first be identified. FIG. 3 is a perspective view, partially cut away, showing the typical cell-to-cell arrangement of the MOSFET array 24. FIG. 4 is the top plan view taken along the line 4--4 of FIG. 3. FIGS. 3 and 4 are shown with the insulating and passivation layers removed exposing the relevant layers of the MOSFET array 24. The cell-to-cell arrangement of the array shown in FIGS. 3 and 4 are called the "brick wall" pattern in which the cells of any cell row are shifted by half a cell length with respect to the cells of the adjacent cell rows. Alternatively, the cells can be arranged in another pattern called the "waffle" pattern in which the cell rows and columns are geometrically aligned as shown in FIG. 5.
As another alternative, cells can be arranged in a "honey comb" pattern as disclosed in U.S. Pat. No. 5,072,266, Bulucea et al., entitled "Trench DMOS Power Transistor with Field-Shaping Body Profile and Three-Dimensional Geometry", issued Dec. 10, 1991. The "honey comb" pattern is illustrated in FIG. 6.
To alleviate the aforementioned problems of shrinkage in contact areas for the source regions 36 and the cell contact regions 52 (FIG. 2) due to dense integration, it is desirable that the power-on resistance R.sub.ON resistance decreases without any accompanying reduction in the source contact and cell contact areas associated with the regions 36 and 52. Phrased differently, with reference to FIGS. 1 and 2, in the fabrication of a high density MOSFET array with the state-of-the art high resolution photolithography, the ideal objective is to reduce the drain-to-source resistance R.sub.DS of each cell 19 or 34 without any concomitant increase in the source contact resistance R.sub.CS and the cell contact resistance R.sub.CC.
The semiconductor array of the invention accomplishes the above-mentioned objective by extracting a longer cell boundary out of a fixed cell area. A longer cell boundary results in a longer channel width W for each cell 34 which in turn provides lower drain-to-source resistance R.sub.DS.
As is known in the art, the power-on resistance R.sub.ON assumes the following algebraic relationship: ##EQU1## where L is the channel length in .mu.m; and W is the channel width in .mu.m. With reference again to FIGS. 2-5, for a trenched MOSFET with a square cell configuration, the channel length L is the linear dimension extending from source region 36 to the epitaxial region 40 (FIG. 3). The channel width W is the length of the boundary enclosing each active cell 34. Each side of the square cell 34 is one quarter of the channel width W and is labelled W/4 in FIGS. 3-5.
Assuming the channel length L is a fixed parameter, and further assuming that the geometrical area for each cell 34 is also fixed such that there is no diminution in the area L sizes of the source regions 36 and the cell contact regions 52, a MOSFET cell with a lower power-on resistance R.sub.ON would result if a longer channel W can be designed to encompass each cell 34. The MOSFET array of the invention provides such a longer channel width W for each cell without any sacrifice or trade-offs with other parameters.
Instruments are now built with ever increasing complexity and decreasing physical sizes. To fully reap the advantages of high resolution photolithography, factors that hamper high density integration must be overcome. Specifically, semiconductor power devices, even fabricated with fine line geometry at high packing density, need to exhibit ruggedness in performance and with low power-on resistance. At the same time, production yield is not compromised with the improvement in performance. There has been a long-felt need to provide power devices meeting the aforementioned criteria.